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| SSM4502GM N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET PRODUCT SUMMARY D2 D2 D1 D1 G2 N-CH BVDSS RDS(ON) ID S2 G1 20V 18m 8.3A -20V 45m -5A Simple Drive Requirement Low Gate Charge Fast Switching Performance P-CH BVDSS RDS(ON) ID SO-8 S1 DESCRIPTION The advanced power MOSFETs from Silicon Standard Corp. provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SO-8 package is widly preferred for commercial-industrial surface mount applications and suited for low voltage applications such as DC/DC converters. D1 D2 Pb-free; RoHS-compliant G1 S1 G2 S2 ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID@TA=25 ID@TA=70 IDM PD@TA=25 TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating N-channel 20 12 8.3 6.5 30 2.0 0.016 -55 to 150 -55 to 150 P-channel -20 12 -5 -4 -20 Units V V A A A W W/ Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rthj-a Parameter Maximum Thermal Resistance, Junction-ambient 3 Value 62.5 Unit /W 02/13/2008 Rev.1.00 www.SiliconStandard.com 1 SSM4502GM N-CH Electrical Characteristics@Tj=25oC(unless otherwise specified) Symbol BVDSS RDS(ON) Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance 2 Test Conditions VGS=0V, ID=250uA VGS=10V, ID=9A VGS=4.5V, ID=8.3A VGS=2.5V, ID=5.2A Min. 20 0.5 - Typ. 8.3 22 3 9 11 13 30 14 1350 325 255 Max. Units 16 18 30 1 25 100 V m m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70oC) o VDS=VGS, ID=250uA VDS=10V, ID=8.3A VDS=20V, VGS=0V VDS=16V ,VGS=0V VGS=12V ID=8A VDS=16V VGS=4.5V VDS=10V ID=1A RG=3.3,VGS=5V RD=10 VGS=0V VDS=20V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 SOURCE-DRAIN DIODE Symbol VSD trr Qrr Parameter Forward On Voltage 2 2 Test Conditions IS=1.8A, VGS=0V IS=8A, VGS=0V, dI/dt=100A/s Min. - Typ. 32 24 Max. Units 1.2 V ns nC Reverse Recovery Time Reverse Recovery Charge 02/13/2008 Rev.1.00 www.SiliconStandard.com 2 SSM4502GM P-CH Electrical Characteristics@Tj=25oC(unless otherwise specified) Symbol BVDSS RDS(ON) Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance 2 Test Conditions VGS=0V, ID=-250uA VGS=-10V, ID=-6A VGS=-4.5V, ID=-5A VGS=-2.5V, ID=-4A Min. -20 -0.5 - Typ. 2.2 13 1.5 4.5 8 17 24 36 920 90 85 Max. Units 40 45 80 -1 -25 100 V m m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=-250uA VDS=-10V, ID=-2.2A VDS=-20V, VGS=0V VDS=-16V, VGS=0V VGS=12V ID=-5A VDS=-16V VGS=-4.5V VDS=-10V ID=-1A RG=3.3,VGS=-5V RD=10 VGS=0V VDS=-20V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 SOURCE-DRAIN DIODE Symbol VSD trr Qrr Parameter Forward On Voltage 2 Test Conditions IS=-1.8A, VGS=0V IS=-5A, VGS=0V, dI/dt=100A/s Min. - Typ. 28 16 Max. -1.2 - 30 V ns nC Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by Max. junction temperature. 2.Pulse test 3.Surface mounted on 1 in2 copper pad of FR4 board ; 135 /W when mounted on Min. copper pad. THIS PRODUCT IS AN ELECTROSTATIC SENSITIVE, PLEASE HANDLE WITH CAUTION. THIS PRODUCT HAS BEEN QUALIFIED FOR CONSUMER MARKET. APPLICATIONS OR USES AS CRITERIAL COMPONENT IN LIFE SUPPORT DEVICE OR SYSTEM ARE NOT AUTHORIZED. 02/13/2008 Rev.1.00 www.SiliconStandard.com 3 SSM4502GM N-Channel 30 30 T A =25 ID , Drain Current (A) ID , Drain Current (A) 5.0V 4.5V 3.5V 2.5V T A =150 5.0V 4.5V 3.5V 2.5V 20 20 V G = 2.0 V V G =2.0V 10 10 0 0 1 2 3 0 0 1 2 3 4 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics 34 1.8 Fig 2. Typical Output Characteristics I D =8.3A V G =10V I D = 5.2A 30 T A = 25 o C Normalized R DS(ON) RDS(ON0 (m) 26 1.4 22 18 1.0 14 30 0.6 1 2 3 4 5 -50 0 -30 50 100 150 10 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( o C) Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 02/13/2008 Rev.1.00 www.SiliconStandard.com 4 SSM4502GM N-Channel 10 2.0 8 1.6 6 Normalized VGS(th) (V) 1.2 1.4 1.2 IS(A) T j =150 o C 4 T j =25 o C 0.8 2 0.4 0 0 0.2 0.4 0.6 0.8 1 0.0 -50 0 50 100 150 V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C) o Fig 5. Forward Characteristic of Reverse Diode Fig 6. Gate Threshold Voltage v.s. Junction Temperature 02/13/2008 Rev.1.00 www.SiliconStandard.com 5 SSM4502GM N-Channel 12 10000 f=1.0MHz VGS , Gate to Source Voltage (V) 10 ID=8A V DS = 10 V 8 1000 C iss C oss C rss 6 C (pF) 100 10 4 2 0 0 10 20 30 40 50 1 5 9 13 17 21 25 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 100us 10 Normalized Thermal Response (R thja) 0.2 1ms ID (A) 1 0.1 0.1 0.05 10ms 100ms 0.02 0.01 PDM 0.01 t T Single Pulse 0.1 1s T A =25 C Single Pulse o DC 1 10 100 30 0.001 0.0001 0.001 0.01 0.1 -30 1 Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=135 oC/W 0.01 0.1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance 02/13/2008 Rev.1.00 www.SiliconStandard.com 6 SSM4502GM N-Channel VDS 90% VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform 02/13/2008 Rev.1.00 www.SiliconStandard.com 7 SSM4502GM P-Channel 20 20 T A =25 o C 16 -ID , Drain Current (A) 12 -ID , Drain Current (A) - 5.0 V - 4.5 V - 3.5 V - 2.5 V V G = - 1.5 V T A = 150 o C 16 -5.0 V - 4.5 V - 3.5 V - 2.5 V 12 V G = - 1.5 V 8 8 4 4 0 0 1 2 3 4 5 0 0 1 2 3 4 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 60 1.4 I D = -5.7 A T A =25 o C 56 1.2 I D = -5.7 A V G = - 10V Normalized R DS(ON) RDS(ON) (m) 52 1.0 48 0.8 44 30 40 1 2 3 4 5 -30 0 50 100 150 0.6 -50 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance v.s. Gate Voltage Fig 4. Normalized On-Resistance v.s. Junction Temperature 02/13/2008 Rev.1.00 www.SiliconStandard.com 8 SSM4502GM P-Channel 8 1.2 Normalized -VGS(th) (V) 1.2 1.4 6 1.0 -IS(A) 4 T j =150 o C T j =25 o C 0.8 2 0 0.6 0 0.2 0.4 0.6 0.8 1 -50 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( o C) Fig 5. Forward Characteristic of Reverse Diode Fig 6. Gate Threshold Voltage v.s. Junction Temperature 02/13/2008 Rev.1.00 www.SiliconStandard.com 9 SSM4502GM P-Channel 12 10000 f=1.0MHz -VGS , Gate to Source Voltage (V) 9 6 C (pF) I D = -5A V DS = -16V 1000 C iss 100 3 C oss C rss 0 0.0 5.0 10.0 15.0 20.0 25.0 30.0 10 1 5 9 13 17 21 25 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Normalized Thermal Response (R thja) Duty factor=0.5 10 -ID (A) 100us 1ms 1 0.2 10ms 100ms 1s 0.1 0.1 0.05 PDM t T 0.02 0.1 T A =25 o C Single Pulse 0.01 0.1 1 10 DC 30 0.01 Single Pulse -30 0.001 0.01 0.1 1 Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=135 oC/W 0.01 100 0.0001 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance 02/13/2008 Rev.1.00 www.SiliconStandard.com 10 SSM4502GM P-Channel VDS 90% VG QG -4.5V QGS 10% VGS td(on) tr td(off) tf Charge Q QGD Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform 02/13/2008 Rev.1.00 www.SiliconStandard.com 11 SSM4502GM Package Outline : SO-8 D SYMBOLS Millimeters MIN NOM MAX A 8 7 6 5 E 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.38 0 1.55 0.18 0.41 0.22 4.90 3.90 6.15 0.71 4.00 1.27 TYP 1.75 0.25 0.51 0.25 5.00 4.00 6.50 1.27 8.00 A1 B E1 C D E1 E L 1 2 3 4 e B e A A1 DETAIL A L 1.All Dimension Are In Millimeters. 2.Dimension Does Not Include Mold Protrusions. c DETAIL A 02/13/2008 Rev.1.00 www.SiliconStandard.com 12 SSM4502GM Part Marking Information & Packing : SO-8 Part Number Package Code meet Rohs requirement 4502GM YWWSSS Date Code (YWWSSS) YLast Digit Of The Year WWWeek SSSSequence Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 02/13/2008 Rev.1.00 www.SiliconStandard.com 13 |
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